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Integrated Circuit Systems, Inc.
ICS1574B
User Programmable Laser Engine Pixel Clock Generator
Description
The ICS1574B is a very high performance monolithic phaselocked loop (PLL) frequency synthesizer designed for laser engine applications. Utilizing ICS's advanced CMOS mixedmode technology, the ICS1574B provides a low cost solution for high-end pixel clock generation for a variety of laser engine product applications. The pixel clock output (PCLK) frequency is derived from the main clock by a programmable resettable divider. Operating frequencies are fully programmable with direct control provided for reference divider, feedback divider and post-scaler.
Features *
Supports high resolution laser graphics. PLL/VCO frequency re-programmable through serial interface port to 400 MHz; allows less than 1.5ns pixel clock resolution. Laser pixel clock output is synchronized with conditioned beam detect input Ideal for laser printer, copier and FAX pixel clock applications On-chip PLL with internal loop filter On-chip XTAL oscillator frequency reference Resettable, programmable counter gives glitch-free clock alignment Single 5 volt power supply Low power CMOS technology Compact - 16-pin 0.150" skinny SOIC package User re-programmable clock frequency supports zoom and gray scale functions
* * * * * * * * *
Block Diagram
Figure 1
1574B 8/31/00
ICS1574B
Pin Configuration
PCLKEN XTAL1 XTAL2 DATCLK VSS VSS PCLK
(Do Not Connect) Reserved
1 2
16 15
DATA HOLD TEST (Connect to VSS)) VDD VDDO Reserved (Do Not Connect) Reserved (Do Not Connect) Reserved (Do Not Connect)
ICS1574B
2
3 4 5 6 7 8
14 13 12 11 10 9
16-Pin Skinny SOIC Pin Descriptions
PIN NUMBER 7 1 2 3 4 16 15 14 8, 9, 10, 11 13 12 5, 6 P I N NA M E PCLK PCLKEN X TA L 1 X TA L 2 DAT C L K DATA HOLD Te s t R e s e r ve d VDD VDDO VSS DESCRIPTION P i xe l c l o c k o u t p u t . PCLK Enable (Input). Q u a r t z c r y s t a l c o n n e c t i o n 1 / ex t e r n a l r e f e r e n c e f r e q u e n cy i n p u t . Quartz crystal connection 2. Data Clock (Input). S e r i a l R eg i s t e r D a t a ( I n p u t ) . HOLD (Input). Test. (Must be connected to VSS.) R e s e r ve d . ( D o N o t C o n n e c t . ) PLL system power (+5V. See application diagram). Output stage power (+5V). Device ground. (Both pins must be connected.)
ICS1574B
PCLK Programmable Divider
The ICS1574B has a programmable divider (referred to in Figure 1 as the PCLK divider) that is used to generate the PCLK clock frequency for the pixel clock output. The modulus of this divider may be set to 3, 4, 5, 6, 8, 10, 12, 16 or 20 under register control. The design of this divider permits the output duty factor to be 50/50, even when an odd modulus is selected. The input frequency to this divider is the output of the PLL post-scaler described below: The phase of the PCLK output is aligned with the internal high frequency PLL clock (FVCO) immediately after the assertion of the PCLKEN input pulse (active low if PCLKEN_POL bit is 0 or active high if PCLKEN_POL bit is 1). When PCLKEN is deasserted, the PCLK output will complete its current cycle and remain at VDD until the next PCLKEN pulse. The minimum time PCLKEN must be disabled (TPULSE) is 1/FPCLK. See Figure 2a for an example of PCLKEN enable (negative polarity) vs. PCLK timing sequences.
TK = K * TVCO
Td = LOGIC PROP.DELAY TIME (typically 9ns with a 10pF load on PCLK) TVCO = 1/FVCO
Figure 2b
The resolution of Ton is one VCO cycle.
The time required for a PCLK cycle start following a PCLKEN enable is described by Figure 2b and the following table:
K Va l u e s P C L K D iv i d e r
3 4a 4b 5 6 8a 8b 10 12 16a 16b 20
K
2 3.5 3 4.5 3.5 5.5 5 7 6.5 9.5 9 12
Figure 2a
Typical values for Tr and Tf with a 10pF load on PCLK are 1ns.
3
ICS1574B
PLL Post-Scaler
A programmable post-scaler may be inserted between the VCO and the PCLK divider of the ICS1574B. This is useful in generating lower frequencies, as the VCO has been optimized for high-frequency operation. The post-scaler is not affected by the PCLKEN input. The post-scaler allows the selection of: * VCO frequency * VCO frequency divided by 2 * VCO frequency divided by 4 * AUX-EN Test Mode back divider makes use of a dual-modulus prescaler technique that allows the programmable counters to operate at low speed without sacrificing resolution. This is an improvement over conventional fixed prescaler architectures that typically impose a factor-of-four (or larger) penalty in this respect. Table 1 permits the derivation of "A" & "M" converter programming directly from desired modulus.
Digital Inputs
The programming of the ICS1574B is performed serially by using the DATCLK, DATA, and HOLD pins to load an internal shift register. DATA is shifted into the register on the rising edge of DATCLK. The logic value on the HOLD pin is latched at the same time. When HOLD is low, the shift register may be loaded without disturbing the operation of the ICS1574B. When high, the shift register outputs are transferred to the control registers, and the new programming information becomes active. Ordinarily, a high level should be placed on the HOLD pin when the last data bit is presented. See Figure 3 for the programming sequence. The PCLKEN input polarity may be programmed under register control via Bit 39.
PLL Synthesizer Description -- Ratiometric Mode
The ICS1574B generates its output frequencies using phaselocked loop techniques. The phase-locked loop (or PLL) is a closed-loop feedback system that drives the output frequency to be ratiometrically related to the reference frequency provided to the PLL (see Figure 1). The reference frequency is generated by an on-chip crystal oscillator or the reference frequency may be applied to the ICS1574B from an external frequency source. The phase-frequency detector shown in the block diagram drives the voltage-controlled oscillator, or VCO, to a frequency that will cause the two inputs to the phase-frequency detector to be matched in frequency and phase. This occurs when:
F(VCO): = F(XTAL1) * Feedback Divider
Reference Divider
This expression is exact; that is, the accuracy of the output frequency depends solely on the reference frequency provided to the part (assuming correctly programmed dividers). The VCO gain is programmable, permitting the ICS1574B to be optimized for best performance at all operating frequencies. The reference divider may be programmed for any modulus from 1 to 128 in steps of one. The feedback divider may be programmed for any modulus from 37 through 392 in steps of one. Any even modulus from 392 through 784 can also be achieved by setting the "double" bit which doubles the feedback divider modulus. The feed-
Figure 3 Output Description
The PCLK output is a high-current CMOS type drive whose frequency is controlled by a programmable divider that may be selected for a modulus of 3, 4, 5, 6, 8, 10, 12, 16 or 20. It may also be suppressed under register control via Bit 46.
4
ICS1574B
Reference Oscillator and Crystal Selection
The ICS1574B has circuitry on-board to implement a Pierce oscillator with the addition of only one external component, a quartz crystal. Pierce oscillators operate the crystal in anti- (also called parallel-) resonant mode. See the AC Characteristics for the effective capacitive loading to specify when ordering crystals. Series-resonant crystals may also be used with the ICS1574B. Be aware that the oscillation frequency will be slightly higher than the frequency that is stamped on the can (typically 0.025 - 0.05%). As the entire operation of the phase-locked loop depends on having a stable reference frequency, we recommend that the crystal be mounted as closely as possible to the package. Avoid routing digital signals or the ICS1574B outputs underneath or near these traces. It is also desirable to ground the crystal can to the ground plane, if possible. If an external reference frequency source is to be used with the ICS1574B, it is important that it be jitter-free. The rising and falling edges of that signal should be fast and free of noise for best results. The loop phase can be locked to either the rising or falling edges of the XTAL1 input signals, and is controlled by Bit 56.
Programming Notes
* *
VCO Frequency Range: Use the post-divider to keep the VCO frequency as high as possible within its operating range. Divider Range: For best results in normal situations keep the reference divider modulus as short as possible (for a frequency at the output of the reference divider in the few hundred kHz to several MHz range). If you need to go to a lower phase comparator reference frequency (usually required for increased frequency accuracy), that is acceptable, but jitter performance will suffer somewhat. VCO Gain Programming: Use the minimum gain which can reliably achieve the VCO frequency desired, as shown here:
*
VCO GAI N 4 5 6 7
MA X F R E QU E N C Y 100 MHz 200 MHz 300 MHz 400 MHz
*
Power-On Initialization
The ICS1574B has an internal power-on reset circuit that performs the following functions: 1) Selects the modulus of the PCLK divider to be four (4). 2) Sets the multiplexer to pass the reference frequency to PCLK divider input. These functions should allow initialization for most applications that cannot immediately provide for register programming upon system power-up. Because the power-on reset circuit is on the VDD supply, and because that supply is filtered, care must be taken to allow the reset to de-assert before programming. A safe guideline is to allow 20 microseconds after the VDD supply reaches 4 volts.
Phase Detector Gain: For most applications and divider ranges, set P [1, 0] = 10 and set P[2] = 1. Under some circumstances, setting the P [2] bit "on" can reduce jitter. During operation at exact multiples of the crystal frequency, P[2] bit = 0 may provide the best jitter performance.
Board Test Support
It is often desirable to statically control the levels of the output pins for circuit board test. The ICS1574B supports this through a register programmable mode, AUX-EN. When this mode is set, a register bit directly controls the logic level of the PCLK pin. This mode is activated when the S[0] and S[1] bits are both set to logic 1. See Register Mapping for details.
5
ICS1574B
Power Supplies and Decoupling
The ICS1574B has two VSS pins to reduce the effects of package inductance. Both pins are connected to the same potential on the die (the ground bus). BOTH of these pins should connect to the ground plane of the PCB as close to the package as is possible. The ICS1574B has a VDDO pin which is the supply of +5 volt power to the output driver. This pin should be connected to the power plane (or bus) using standard high-frequency decoupling practice. That is, capacitors should have low series inductance and be mounted close to the ICS1574B. The VDD pin is the power supply pin for the PLL synthesizer circuitry and other lower current digital functions. We recommend that RC decoupling or zener regulation be provided for this pin (as shown in the recommended application circuitry). This will allow the PLL to "track" through power supply fluctuations without visible effects. See Figure 4 for typical external circuitry.
Figure 4
6
ICS1574B
Register Mapping -- ICS1574B
NOTE: It is not necessary to understand the function of these bits to use the ICS1574B. PC Software is available from ICS to
automatically generate all register values based on requirements. Contact factory for details.
BIT(S)
1-4
BIT REF.
PCLK[0]..PCLK[3]
DESCRIPTION
Sets PCLK divider modulus according to this table. These bits are set to implement a divide-by-four on power-up.
PCLK[ 3] 0 0 0 0 0 0 0 0 1 1 1 1 PCLK[ 2] 0 0 0 0 1 1 1 1 X X X X PCLK[ 1] 0 0 1 1 0 0 1 1 0 0 1 1 PCLK[ 0] 0 1 0 1 0 1 0 1 0 1 0 1 MODUL US 3 4( a ) 4( b) 5 6 8( a ) 8( b) 10 12 16( a ) 16( b) 20
(X = Don't Care)
5, 6 7 8
Reserved Reserved SELXTAL
Must be set to 0. Must be set to 1. Normally set to 0. When set to logic 1, passes the reference frequency to the post-scaler instead of the PLL output (defaults to 1 on power-up). Must be set to 0. Must be set to 1. Must be set to 0. PLL post-scaler / test mode select bits.
S[1] 0 0 1 1 S[0] 0 1 0 1 DESCRI PTI ON
Post-scaler = 1. F(CLK) = F(PLL). The output of the PCLK divider drives the PCLK output. Post-scaler = 2. F(CLK) = F(PLL)/2. The output of the PCLK divider drives the PCLK output. Post-scaler = 4. F(CLK) = F(PLL)/4. The output of the PCLK divider drives the PCLK output. AUX-EN TEST MODE. The AUX_PCLK bit drives the PCLK output.
9 10 11, 12 13 - 14
Reserved Reserved Reserved S[0]..S[1]
7
ICS1574B
BIT(S)
15 16
BIT REF.
Reserved
DESCRIPTION
Must be set to 0.
AUX_PCLK Must be set to 0 except when in the AUX-EN test mode. When in the AUX-EN test mode, this bit controls the PCLK output. Reserved V[0]..V[2] Must be set to 0. Sets the gain of VCO
V[ 2] 1 1 1 1 V[ 1] 0 0 1 1 V[ 0] 0 1 0 1 VCO GAI N
( MHz / Vo l t )
17 - 24 25 - 27
30 45 60 80
28 29 - 30
Reserved P[0]..P[1]
Must be set to 1. Sets the gain of the phase detector according to this table:
P[1] 0 0 1 1 P[0] 0 1 0 1 GAI N ( A/ r a di a n) 0. 05 0. 15 0. 5 1. 5
31 32 33 - 38 39
Reserved P[2] See text. M[0]..M[5] PCLKEN_POL
Must be set to 0. Phase detector tuning bit. Should normally be set to one. M counter control bits. Modulus = value + 1. When = 0, PCLK output enabled when PCLKEN input is low. When = 1, PCLK output enabled when PCLKEN input is high. Doubles modulus of dual-modulus prescaler (from 6 / 7 to Controls A counter. When set to zero, modulus = 7. Otherwise, modulus = 7 for "value" underflows of the prescaler, and modulus = 6 thereafter until M counter underflows.
40 41 - 44
DBLFREQ 12 /14). A[0]..A[3]
8
ICS1574B
BIT(S)
45 46
BIT REF.
Reserved PCLK_EN
DESCRIPTION
Must be set to 1. Must be set to 0. Disables the PCLK divider when set to 1 regardless of PCLKEN input state. Must be set to 0. Reference divider modulus control bits. Modulus = value +1. PLL locks to rising edge of XTAL1 input when REFPOL = 1, falling edge of XTAL1 when REFPOL = 0.
47, 48 49 - 55 56
Reserved R[0]..R[6] REF_POL
9
ICS1574B
Table 1 -- "A" & "M" Divider Programming Feedback Divider Modulus Table
A[2]..A[0]- 001 M[5]..M[0] 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 13 19 25 31 37 43 49 55 61 67 73 79 85 91 97 103 109 115 127 133 139 145 157 163 169 175 187 193 20 26 32 38 44 50 56 62 68 74 80 86 92 98 104 110 116 128 134 140 146 158 164 170 176 188 194 27 33 39 45 51 57 63 69 75 81 87 93 99 105 117 123 129 135 147 153 159 165 177 183 189 195 34 40 46 52 58 64 70 76 82 88 94 100 106 118 124 130 136 148 154 160 166 178 184 190 196 41 47 53 59 65 71 77 83 89 95 107 113 119 125 137 143 149 155 167 173 179 185 197 48 54 60 66 72 78 84 90 96 108 114 120 126 138 144 150 156 168 174 180 186 198 55 61 67 73 79 85 91 97 103 109 115 121 127 133 139 145 151 157 163 169 175 7 14 21 28 35 42 49 56 63 70 77 84 91 98 105 112 119 126 133 140 147 154 161 168 175 182 189 196 010 011 100 101 110 111 000 A[2]..A[0]- 001 M[5]..M[0] 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111000 111001 111010 111011 111100 111101 111110 111111 199 200 205 217 223 229 235 247 253 259 265 277 283 289 295 307 313 319 325 337 343 349 355 367 373 379 385 206 218 224 230 236 248 254 260 266 278 284 290 296 308 314 320 326 338 344 350 356 368 374 380 386 211 212 201 202 207 213 219 225 237 243 249 255 267 273 279 285 297 303 309 315 327 333 339 345 357 363 369 375 387 208 214 220 226 238 244 250 256 268 274 280 286 298 304 310 316 328 334 340 346 358 364 370 376 388 203 209 215 227 233 239 245 257 263 269 275 287 293 299 305 317 323 329 335 347 353 359 365 377 383 389 204 210 216 228 234 240 246 258 264 270 276 288 294 300 306 318 324 330 336 348 354 360 366 378 384 390 205 211 217 223 229 235 241 247 253 259 265 271 277 283 289 295 301 307 313 319 325 331 337 343 349 355 367 373 379 385 231 238 245 252 259 266 273 280 287 294 301 308 315 322 329 336 343 350 357 364 371 378 385 392 399 406 420 427 434 441 010 011 100 101 110 111 000
221 222
231 232
241 242
251 252
261 262
271 272
281 282
101 102
291 292
111 112
301 302
311 312
121 122
131 132
321 322
141 142
331 332
341 342
151 152
161 162
351 352
361 413
171 172
361 362
181 203 187 210 193 217 199 224
371 372
181 182
191 192
381 382
391 448
Notes: To use this table, find the desired modulus in the table. Follow the column up to find the A divider programming values. Follow the row to the left to find the M divider programming. Some feedback divisors can be achieved with two or three combinations of divider settings. Any are acceptable for use. The formula for the effective feedback modulus is: except when A=0, then: Under all circumstances: N =[(M +1) * 6] +A N=(M +1) * 7 AM
10
ICS1574B
Absolute Maximum Ratings
VDD, VDDO (measured to VSS) . . . . . . . . Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . Digital Outputs . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . Junction Temperature . . . . . . . . . . . . . . . . . Soldering Temperature . . . . . . . . . . . . . . . . 7.0 V VSS - 0.5 V to VDD +0.5V VSS - 0.5V to VDD O +0.5V - 55 C to +125 C - 65 C to +150 C 175 C 260 C
Recommended Operating Conditions
VDD, VDDO (measured to VSS) . . . . . . . . 4.75 to 5.25 V Operating Temperature (Ambient) . . . . . . 0 to +70C
DC Electrical Characteristics
TTL-Compatible Inputs (DATCLK, DATA, HOLD, PCLKEN)
PARAME T E R Input High Voltage Input Low Voltage Input High Current Input Low Current Input Capacitance Hysterisis (DATCLK input) S YMB OL VIH VIL I IH I IL CIN V HYS CONDI TI ONS MI N 2. 0 VSS - 0 . 5 -- -- -- . 20 MAX V DD + 0 . 5 0. 8 10 200 8 . 60 UNI TS V V A A pF V
VIH = VDD VIL = 0 . 0 VDD = 5 V
XTAL1 Input (External Reference Frequency)
PARAME T E R Input High Voltage Input Low Voltage S YMB OL V XH V XL CONDI TI ONS MI N 3. 75 VSS - 0 . 5 MAX V DD + 0 . 5 1. 25 UNI TS V V
PCLK
PARAME T E R Output High Voltage (IOH = 4.0mA) Output Low Voltage (IOL = 8.0mA) S YMB OL CONDI TI ONS MI N 2. 4 -- MAX -- 0. 4 UNI TS V V
11
ICS1574B
AC Electrical Characteristics
PARAME T E R VCO Frequency Crystal Frequency Crystal Oscillator Loading Capacitance XTAL1 High Time (when driven externally) XTAL1 Low Time (when driven externally) PLL Acquire Time (to within 1%) VDD Supply Current VDDO Supply Current DATA/HOLD ~Setup Time DATA/HOLD ~Hold Time DATCLK Pulse Width (Thi or Tlo) PCLK output rate F P CLOCK S YMB OL F VCO FXTAL CPAR T XHI T XLO T LOCK I DD I DDO MI N 40 5 8 8 500 15 20 10 10 20 t . b. d. t . b. d. TYP MAX 400 20 UNI TS MHz MHz pF ns ns s mA mA ns ns ns 130 MHz
20
Digital Inputs
Digital Output
16-Pin Skinny SOIC Package Ordering Information
ICS1574BM / ICS1574BEB
Example:
ICS 1574B M
Package Type M = SOIC * Device Type
EB = Evaluation Board
Prefix ICS, AV = Standard Device * GSP = Genlock Device
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